Cache Coherent Interconnect IP for Machine Learning SoCs

Cache Coherent Interconnect IP for Machine Learning SoCs

A new interconnect IP takes on processing and functional safety challenges in chipsets designed for ADAS and autonomous vehicle systems. ArterisIP has announced the availability of the Ncore 2.0 Cache Coherent Interconnect IP that, according to the company, allows system-on-chip (SoC) designers to easily integrate custom processing elements using low-latency proxy caches or I/O caches.